A 3D IC package contains two or more integrated circuit dies (ICs) stacked vertically so that they occupy less space. Connections between the vertically stacked ICs may be made using through-semiconductor-vias, also referred to as through-silicon-vias (TSV), which pass through the entire thickness of a die, permitting connections between conductive patterns on the front face and back face of the die. The resulting package has no added length or width.
3D IC packages present new challenges for fabrication and verification. Assuming that only known good dies are included in the 3D IC package, one of the stacked dies may be damaged during the packaging process. Once the stacked dies have been incorporated into an encapsulated 3D IC package, it is no longer practical to repair or replace one of the dies.